As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then patterned and etched. The barrier material is then deposited over the structure with the copper being formed over the barrier material. Then, the copper and barrier material are chemically-mechanically polished to remove the conducting material from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided.
The most practical technique for forming copper interconnects is electrochemical deposition (ECD). In this process, after the barrier material is deposited, a seed layer of copper is deposited. Then, ECD is used to deposit copper over the seed layer. ECD is a process used to produce a solid phase product (such as a thin film) by electrochemical reaction. Cu ECD is a process used to make Cu thin films through the electrochemical reduction of Cu ions, represented by the following chemical equation:Cu+++2e−→Cuwhere e− represents electron.In order for the ECD process to proceed, a seed layer is required to pass current and to serve as a nucleation layer. The wettability of the seed surface is very critical for the success of the ECD process. If the plating solution cannot wet the seed surface, no Cu can by deposited on that area of the surface, forming a void.
One of the problems with ECD copper films is that the films frequently show unacceptably high defect levels. The defect concentration is very sensitive to the surface condition. For example, examining wafers prior to ECD by scanning electron microscopy (SEM) can increase the ECD defect concentration due to surface contamination. The surface effect can be traced to wettability of the seed surface with the bath solution. A method for improving the wettability of the seed surface is therefore desired.